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TECHNICAL NOTE
High-performance Clock Generator Series
Clock Generator with Built-in VCXO for Audio/Video Equipments
BU2365FV
Description The ROHM Clock Generator is an IC allowing for the generation of multiple clocks by a single chip through the connection of a single crystal oscillator. The BU2365FV incorporates the ROHM's unique PLL technology to provide the generation of multiple high C/N clocks necessary for the DVD recorder system. This Clock Generator has the built-in high-precision VCXO function and allows for high-precision synchronization with DVD Video clocks. It also has a built-in buffer having high driving force and allows the supply of multiple 27MHz Video clocks for the system, thus providing the reduced number of the system components.
Features 1) The ROHM's unique PLL technology allows for the generation of high C/N clocks. 2) Built-in high precision VCXO, which is essential for the DVD recorder system 3) Built-in buffer having high driving force (Load capacity/output CL=50pF, 27MHz drive, 1xinput / 2xoutputs) 4) Built-in half pulse clock protection [HPC] 5) Built-in power down function, Icc=0 uA(typ.) 6) SSOP-B24 package 7) Single power supply of 3.3 V
Application DVD recorder
Absolute Maximum RatingsTa=25
Parameter Supply voltage Input voltage
Storage temperature range
Symbol VDD VIN Tstg PD
Limit 0.37.0 0.3VDD+0.3 30125 820
Unit mW
Power dissipation
*1 Operation is not guaranteed. *2 In the case of exceeding Ta = 25, 8.2mW should be reduced per 1. *3 The radiation-resistance design is not carried out. *4 Power dissipation is measured when the IC is mounted to the printed circuit board.
Sep. 2008
Recommended Operating Range Parameter Supply voltage Input H voltage Input L voltage Operating temperature Output load 22Pin / 19Pin 13Pin , 14Pin 18Pin / 24Pin
Symbol VDD VINH VINL Topr
Limit 3.03.6 0.8VDDVDD 0.00.2VDD 1070 32(MAX) 50(MAX) 15(MAX)
Unit pF pF pF
CL_CLK768FS/384FS CL_BUFOUT CL_CLK512FS/54M
Electrical characteristics VDD=3.3V, Ta=25, Crystal frequency (XTAL_IN)=27.000000MHz, at no load, unless otherwise specified. Parameter Symbol IDD VOH VOL Pull-Up R Pull-down R Limit Min. 2.4 168 Typ. 55 260 Max. 71.5 0.4 578 Unit mA V V k Condition At no output loads
When current load = -4.0mA When current load =4.0mA
Specified by a current value running when a voltage of 0V is applied to a measuring pin. (R=DD/I) Specified by a current value running
Consumption circuit current Output H voltage Output L voltage
Pull-Up resistance value FSELOE Pull-Down resistance value TEST
31
48
106
k
when a VDD is applied to a measuring pin. (R=VDD/I)
Output frequency CLK768FSFSEL=L CLK768FSFSEL=H CLK384FS CLK512FS CLK54M Output waveform Duty Rise time Fall time Jitter Period-Jitter Period-Jitter 1 MIN-MAX P-J1 P-J MIN-MAX Tlock F/F0 F/Fc Linearity Tskew _BUF Td_BUF 15 30 10 500 4 50 300 45 1 15 60 10 500 8 psec psec msec ppm ppm ppm psec nsec 1 2 3 T=-10 70 VDD=3.3V 0.15V 4 5 5
Phase difference between BUF_OUT1 and BUF_OUT26 Phase difference between BUF_IN and BUF_OUT
CLK768 FS_L CLK768 FS_H CLK384 FS CLK512 FS CLK54M Duty1 Tr Tf
45
33.868800 36.864000 18.432000 24.576000 54.000000 50 2.5 2.5
55
MHz MHz MHz MHz MHz nsec nsec
XTAL_INx(3136/625)/4 XTAL_INx(2048/375)/4 XTAL_INx(2048/375)/8 XTAL_INx(2048/375)/6 XTAL_INx(32/4)/4
Measured at a voltage of 1/2 of VDD Period of time required for the output to reach 80% from 20% of VDD Period of time required for the output to reach 20% from 80% of VDD
Output Lock-Time Frequency stability Frequency sensitivity
Frequency sensitivity linearity
Buffer skew Buffer delay
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to XTAL_IN.
2/16
1 Period-Jitter 1 This parameter represents standard deviation (=1) on cycle distribution data at the time when the output clock cycles are sampled 1000 times consecutively with the TDS7104 Digital Phosphor Oscilloscope of Tektronix Japan, Ltd. 2 Period-Jitter MIN-MAX This parameter represents a maximum distribution width on cycle distribution data at the time when the output clock cycles are sampled 1000 times consecutively with the TDS7104 Digital Phosphor Oscilloscope of Tektronix Japan, Ltd. 3 Output Lock-Time This parameter represents elapsed time after power supply turns ON to reach a voltage of 3.0 V, after the system is switched from Power-Down state to normal operation state, or after the output frequency is switched, until it is stabilized at a specified frequency, respectively. 4 Frequency stability f0 : This parameter means an optimum frequency at T=25(27.000000 MHz), which represents a value of a single piece of IC. Since no consideration is given to the stability of the crystal oscillator, it should be separately studied according to the system in use. 5 Frequency sensitivity/Frequency sensitivity linearity These parameters represents that the frequency falls within the area shown in Fig. 2 in the control circuit of control voltage shown in Fig. 1. It shows the value of IC itself. Since no consideration is given to the stability of the crystal oscillator, it should be separately studied according to the system in use. Common - Recommended crystal oscillators The electrical characteristics shown above have been all evaluated with the use of the crystal oscillator NX5032GA (Spec. No. EXS00A-00278) manufactured by NIHON DEMPA KOGYO CO., LTD., under the conditions of Limiting resistance Rd=30and Crystal oscillator load CL=10pF. Consequently, in order to use the BU2365FV, the said crystal oscillator is recommended.
Vc
R2
R1
9Pin VDD_V 10Pin VCTRL
R1
BU2365FV
R1R2=10.875
Fig.1 Control Circuit of Control Voltage
f/f0 f/f0 +60ppm +45ppm +30ppm +15ppm 0ppm 15ppm 30ppm 45ppm 60ppm fL L Hi-Z H Vc fC fH
Frequency sensitivity dispersion range: fL = 4515ppm, fC = 015ppm, fH = 4515ppm However, frequency sensitivity linearity: 10ppm(fH fC) ( fC fL) 10ppm Fig. 2 Frequency Sensitivity Dispersion Range 6 Buffer skew This parameter is only functional when the BUF_OUT1 and the BUF_OUT2 are driven at the same load capacitance. 3/16
Reference data (Basic data) RBW=1KHz VBW=100Hz 10dBdiv 500psecdiv Fig.4 33.8688MHz Period-Jitter VDD=3.3V,CL=32pF 1.0Vdiv 1.0Vdiv 5.0nsecdiv Fig.3 33.8688MHz output waveform VDD=3.3V,CL=32pF
10KHzdiv Fig.5 33.8688MHz spectrum VDD=3.3V,CL=32pF
RBW=1KHz VBW=100Hz 1.0Vdiv 1.0Vdiv 10dBdiv
5.0nsecdiv Fig.6 36.864MHz output waveform VDD=3.3V,CL=32pF
500psecdiv Fig.7 36.864MHz Period-Jitter VDD=3.3V,CL=32pF
10KHzdiv Fig.8 36.864MHz spectrum VDD=3.3V,CL=32pF
RBW=1KHz VBW=100Hz 1.0Vdiv 10dBdiv 500psecdiv Fig.10 18.432MHz Period-Jitter VDD=3.3V,CL=32pF 1.0Vdiv
10.0nsecdiv Fig.9 18.432MHz output waveform VDD=3.3V,CL=32pF
10KHzdiv Fig.11 18.432MHz spectrum VDD=3.3V,CL=32pF
RBW=1KHz VBW=100Hz 10dBdiv 1.0Vdiv 1.0Vdiv
5.0nsecdiv Fig.12 24.576MHz output waveform VDD=3.3V,CL=15pF
500psecdiv Fig.13 24.576MHz Period-Jitter VDD=3.3V,CL=15pF
10KHzdiv Fig.14 24.576MHz spectrum VDD=3.3V,CL=15pF
4/16
Reference data (Basic data) RBW=1KHz VBW=100Hz 10dBdiv 500psecdiv Fig.16 54MHz Period-Jitter VDD=3.3V,CL=15pF 1.0Vdiv 1.0Vdiv 5.0nsecdiv Fig.15 54MHz output waveform VDD=3.3V,CL=15pF
10KHzdiv Fig.17 54MHz spectrum VDD=3.3V,CL=15pF
RBW=1KHz VBW=100Hz 10dBdiv 1.0Vdiv 1.0Vdiv
5.0nsecdiv Fig.18 BUF_OUT(27MHz) output waveform VDD=3.3V,CL=50pF
500psecdiv Fig.19 BUF_OUT(27MHz) Period-Jitter VDD=3.3V,CL=50pF
10KHzdiv Fig.20 BUF_OUT(27MHz) spectrum VDD=3.3V,CL=50pF
RBW=1KHz VBW=100Hz 10dBdiv 1.0Vdiv 1.0Vdiv
5.0nsecdiv Fig.21 VCXO_OUT(27MHz) output waveform VDD=3.3V,CL=4pF
500psecdiv Fig.22 VCXO_OUT(27MHz) Period-Jitter VDD=3.3V,CL=4pF
10KHzdiv Fig.23 VCXO_OUT(27MHz) spectrum VDD=3.3V,CL=4pF
0.5Vdiv
0.5Vdiv
0.5Vdiv
5.0nsecdiv Fig.24 Buffer skew output waveform VDD=3.3V,CL=50pF
5.0nsecdiv Fig.25 Buffer delay(INOUT1) VDD=3.3V,CL=50pF
5.0nsecdiv Fig.26 Buffer delay(INOUT2) VDD=3.3V,CL=50pF
5/16
Reference data (PLL: 33.8688MHz output
55 54 53 DutyDuty [%] 52 51 50 49 48 47 46 45 -25 0 25 50 75 100 TemperatureT []
VDD=2.9V VDD=3.3V VDD=3.7V
Temperature and Supply voltage variations data)
5 4.5 3.5 3 2.5 2 1.5 1 0.5 0 -25 0 25 50 75 100 TemperatureT []
Fall Time Tf [nsec]
Rise TimeTr [nsec]
4
VDD=2.9V VDD=3.3V VDD=3.7V
5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -25 0 25 50
VDD=2.9V VDD=3.3V VDD=3.7V
75
100
TemperatureT []
Fig.27 33.8688MHz TemperatureDuty
100 Period-Jitter 1P-J1 [psec] 90 70 60 50 40 30 20 10 0 -25 0 25 50 75 100 TemperatureT [] Period-Jitter MIN-MAX P-JMIN-MAX [psec] 80
VDD=2.9V VDD=3.3V VDD=3.7V
Fig.28 33.8688MHz Temperaturerise-time
600 500 400 300 200 100 0 -25 0 25 50 75 100 TemperatureT []
VDD=3.7V VDD=2.9V VDD=3.3V
Fig.29 33.8688MHz Temperaturefall-time
Fig.30 33.8688MHz TemperaturePeriod-Jitter 1 Reference ) data (PLL: 36.864MHz output
55 54 53 DutyDuty [%] 52 51 50 49 48 47 46 45 -25 0 25 50 75 100 TemperatureT []
VDD=2.9V VDD=3.3V VDD=3.7V
Fig.31 33.8688MHz TemperaturePeriod-Jitter MIN-MAX Temperature and Supply voltage variations data)
5 4.5 Rise TimeTr [nsec] Fall TimeTf [nsec] 4 3.5 3 2.5 2 1.5 1 0.5 0 -25 0 25 50 75 100 TemperatureT []
VDD=2.9V VDD=3.3V VDD=3.7V
5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -25 0 25 50 75 100 TemperatureT []
VDD=2.9V VDD=3.3V VDD=3.7V
Fig.32 36.864MHz TemperatureDuty
100 Period-Jitter 1P-J1 [psec] 90 70 60 50 40 30 20 10 0 -25 0 25 50 75 100 TemperatureT [] Period-Jitter MIN-MAX P-JMIN-MAX [psec] 80
VDD=2.9V VDD=3.3V VDD=3.7V
Fig.33 36.864MHz Temperaturerise-time
600 500 400 300 200 100 0 -25 0 25 50 75 100 TemperatureT []
VDD=2.9V VDD=3.7V VDD=3.3V
Fig.34 36.864MHz Temperaturefall-time
Fig.35 36.864MHz TemperaturePeriod-Jitter 1
Fig.36 36.864MHz TemperaturePeriod-Jitter MIN-MAX
6/16
Reference data (PLL: 18.432MHz output
55 54 53 52 51 50 49 48 47 46 45 -25 0 25 50
Temperature and Supply voltage variations data)
5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -25 0 25 50 75 100 TemperatureT []
VDD=2.9V VDD=3.3V VDD=3.7V
5 4.5 Fall TimeTf [nsec] 4 3.5 3 2.5 2 1.5 1 0.5 0 -25 0 25 50 75 100 TemperatureT []
VDD=2.9V VDD=3.3V VDD=3.7V
Duty Duty [%]
VDD=3.3V VDD=2.9V VDD=3.7V
75
100
TemperatureT []
Rise TimeTr [nsec]
Fig.37 18.432MHz TemperatureDuty
100 Period-Jitter 1P-J1 [psec] 90 80 70 60 50 40 30 20 10 0 -25 0 25 50 75 100 TemperatureT [] Period-Jitter MIN-MAX P-JMIN-MAX [psec]
VDD=2.9V VDD=3.3V VDD=3.7V
Fig.38 18.432MHz Temperaturerise-time
600 500 400 300 200 100 0 -25 0 25 50 75 100 TemperatureT []
VDD=2.9V VDD=3.3V VDD=3.7V
Fig.39 18.432MHz Temperaturefall-time
Fig.40 18.432MHz TemperaturePeriod-Jitter
1
Fig.41 18.432MHz TemperaturePeriod-Jitter MIN-MAX Temperature and Supply voltage variations data)
5 4.5 Rise TimeTr [nsec] 4 3.5 3 2.5 2 1.5 1 0.5 0
VDD=2.9V VDD=3.3V VDD=3.7V
Reference data (PLL: 24.576MHz output
55 54 53 DutyDuty [%] 52 51 50 49 48 47 46 45 -25 0 25 50 75 100 TemperatureT []
VDD=2.9V VDD=3.3V VDD=3.7V
5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -25 0 25 50
Fall Time Tf [nsec]
VDD=2.9V VDD=3.3V VDD=3.7V
-25
0
25
50
75
100
75
100
Fig.42 24.576MHz TemperatureDuty
100 Period-Jitter 1P-J1 [psec] 90 Period-Jitter MIN-MAX P-JMIN-MAX [psec] 80 70 60 50 40 30 20 10 0 -25 0 25 50 75 100 TemperatureT [] 0
VDD=2.9V VDD=3.3V VDD=3.7V
TemperatureT []
TemperatureT []
Fig.43 24.576MHz Temperaturerise-time
600 500 400 300 200 100
VDD=2.9V VDD=3.3V VDD=3.7V
Fig.44 24.576MHz Temperaturefall-time
-25
0
25
50
75
100
Fig.45 24.576MHz TemperaturePeriod-Jitter 1
Fig.46 24.576MHz TemperaturePeriod-Jitter MIN-MAX
TemperatureT []
7/16
Reference data (PLL: 54MHz output
55 54 53 52 51 50 49 48 47 46 45 -25 0 25 50
Temperature and Supply voltage variations data)
5 4.5 Rise TimeTr [nsec] Fall TimeTf [nsec] 4 3.5 3 2.5 2 1.5 1 0.5 0 -25 0 25 50 75 100 TemperatureT []
VDD=2.9V VDD=3.3V VDD=3.7V
5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -25 0 25 50 75 100 TemperatureT []
VDD=2.9V VDD=3.3V VDD=3.7V
Duty Duty [%]
VDD=2.9V VDD=3.3V VDD=3.7V
75
100
TemperatureT []
Fig.47 54MHz TemperatureDuty
100 Period-Jitter 1P-J1 [psec] 90 70 60 50 40 30 20 10 0 -25 0 25 50 75 100 TemperatureT []
VDD=2.9V VDD=3.3V VDD=3.7V
Fig.48 54MHz Temperaturerise-time
600 Period-Jitter MIN-MAX P-JMIN-MAX [psec] 500 400 300 200 100 0 -25 0 25 50 75 100 TemperatureT []
VDD=2.9V VDD=3.3V VDD=3.7V
Fig.49 54MHz Temperaturefall-time
80
Fig.50 54MHz TemperaturePeriod-Jitter 1
Fig.51 54MHz TemperaturePeriod-Jitter MIN-MAX Temperature and Supply voltage variations data)
5
VDD=2.9V VDD=3.3V VDD=3.7V
Reference data (CLOCK-BUFFER : 27MHz output
55 54
Rise Time Tr [nsec]
Fall TimeTf [nsec]
53 DutyDuty [%] 52 51 50 49 48 47 46 45 -25 0 25 50
VDD=2.9V VDD=3.3V VDD=3.7V
5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -25 0 25 50
4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -25 0 25 50
VDD=2.9V VDD=3.3V VDD=3.7V
75
100
75
100
75
100
TemperatureT []
TemperatureT []
TemperatureT []
Fig.52 27MHz BUFFER TemperatureDuty
8 Buffer SkewTskew_BUF [psec] Buffer DelayTd_BUF [nsec] 7 6 5 4 3 2 1 0 -25 0 25 50 75 100 TemperatureT []
VDD=2.9V VDD=3.3V VDD=3.7V
Fig.53 27MHz BUFFER Temperaturerise-time
500 400 300 200 100 0 -100 -200 -300 -400 -500 -25 0 25 50 75 100 TemperatureT []
VDD=2.9V VDD=3.3V VDD=3.7V
Fig.54 27MHz BUFFER Temperaturefall-time
500 Buffer SkewTskew_BUF [psec] 400 300 200 100 0 -100 -200 -300 -400 -500 -25 0 25 50 75 100 TemperatureT []
VDD=2.9V VDD=3.3V VDD=3.7V
Fig.55 27MHz BUFFER TemperatureDelay
Fig.56 27MHz BUFFER Temperature - Skew (BUF_OUT2 Phase Lead)
Fig.57 27MHz BUFFER Temperature - Skew (BUF_OUT2 Phase Delay)
8/16
Reference data (VCXO:27MHz output Temperature and Supply voltage variations data) This data represents the central frequency as a deviation to the optimum frequency of 27.000000MHz.
55 54 53 DutyDuty [%] 52 51 50 49 48 47 46 45 -25 0 25 50 75 100 TemperatureT [] Rise TimeTr [nsec]
VDD=2.9V VDD=3.3V VDD=3.7V
5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -25 0 25 50 75 100 TemperatureT []
VDD=2.9V VDD=3.3V VDD=3.7V
5 4.5 Fall TimeTf [nsec] 4 3.5 3 2.5 2 1.5 1 0.5 0 -25 0 25 50 75 100 TemperatureT []
VDD=2.9V VDD=3.3V VDD=3.7V
Fig.58 27MHz VCXO TemperatureDuty
100 Period-Jitter 1P-J1 [psec] 90 80 70 60 50 40 30 20 10 0 -25 0 25 50 75 100 TemperatureT []
VDD=2.9V VDD=3.7V VDD=3.3V
Fig.59 27MHz VCXO Temperaturerise-time
600 Period-Jitter MIN-MAX P-JMIN-MAX [psec] 500
Center freq.fc [ppm] 15 12 9 6 3 0 -3 -6 -9 -12 -15 -25
Fig.60 27MHz VCXO Temperaturefall-time
400 300 200 100 0 -25 0 25 50 75 100
VDD=2.9V VDD=3.3V VDD=3.7V
VDD=3.15V VDD=3.30V VDD=3.45V
0
25
50
75
100
TemperatureT []
TemperatureT []
Fig.61 27MHz VCXO TemperaturePeriod-Jitter 1
Fig.62 27MHz VCXO TemperaturePeriod-Jitter MIN-MAX
Fig.63 27MHz VCXO Temperature - Central frequency fc
Reference data (VCXO : 27MHz output Control voltage - Frequency data) This data represents the central frequency as a deviation to the optimum frequency of 27.000000MHz.
100 80 Frequencyf [ppm] 60 40 20 0 -20 -40 -60 -80 -100
0 0.55 1.1 1.65 2.2 2.75 3.3
VDD=3.3V
Control VoltageVc [V]
Fig.64 27MHz VCXO Control voltage - Frequency data Reference data (BU2365FV consumption current
100 95 Circuit CurrentIcc [mA] 90 85 80 75 70 65 60 55 50 -25 0 25 50 75 100 TemperatureT []
VDD=3.7V VDD=3.3V VDD=2.9V
Temperature and Supply voltage variations data)
5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -25 0 25 50
Standby Current Iccs [A]
VDD=3.7V VDD=3.3V VDD=2.9V
75
100
TemperatureT []
Fig.65 Maximum Load Operating Circuit Current
Fig.66 Power-down Standby Current 9/16
Reference data (PLL : Long Term Jitter data) This data represents Period-Jitter at the 1000th cycle.
0.5Vdiv
0.5Vdiv
2.0nsecdiv Fig.67 33.8688MHz Long Term Jitter
2.0nsecdiv Fig.68 36.864MHz Long Term Jitter
0.5Vdiv
2.0nsecdiv Fig.69 54MHz Long Term Jitter
Reference data (Period-Jitter MIN-MAX Output load CL dependence data) This data represents the output load up to two times as high as the maximum load of each output. Since the 27-MHz buffer is dependent on the jitter of a clock input, the output is represented by the ratio to the jitter at 50pF.
700 600
Period-Jitter MIN-MAX P-JMIN-MAX [psec] 700
700 Period-Jitter MIN-MAX P-JMIN-MAX [psec]
VDD=3.3V
600 500 400 300 200 100 0 0 10 20 30 40 50 60 70 Output LoadCL [pF]
600 500 400 300 200 100 0 0 10 20 30 40 50 60 70 Output LoadCL [pF]
VDD=3.3V
Period-Jitter MIN-MAX P-JMIN-MAX [psec]
500 400 300 200 100 0 0 10 20 30 40 50 60 70 Output LoadCL [pF]
VDD=3.3V
Fig.70 33.8688MHz CLPeriod-Jitter MIN-MAX
700 Period-Jitter MIN-MAX P-JMIN-MAX [psec] Period-Jitter MIN-MAX P-JMIN-MAX [psec] 600 500 400 300 200 100 0 0 5 10 15 20 25 30 Output LoadCL [pF]
VDD=3.3V
Fig.71 36.864MHz CLPeriod-Jitter MIN-MAX
700 Period-Jitter MIN-MAX P-JMIN-MAX [psec] 600 500 400 300 200 100 0 0 5 10 15 20 25 30 Output LoadCL [pF]
VDD=3.3V
Fig.72 18.432MHz CLPeriod-Jitter MIN-MAX
700 600 500 400 300 200 100 0 0 1 2 3 4 5 6 7 8 Output LoadCL [pF]
VDD=3.3V
Fig.73 24.576MHz CLPeriod-Jitter MIN-MAX
2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 25
Fig.74 54MHz CLPeriod-Jitter MIN-MAX
Fig.75 27MHz VCXO CLPeriod-Jitter MIN-MAX
Period-Jitter MIN-MAX P-JMIN-MAX
VDD=3.3V
50
75
100
Output LoadCL [pF]
Fig.76 27MHz BUFFER CLPeriod-Jitter MIN-MAX 10/16
Block diagram, Pin assignment
3PinFSEL PLL1 1/4 22PinCLK768FS output (FSEL=L33.8688MHz) (FSEL=OPEN36.864MHz)
7PinXTAL_IN 27.0000MHz Crystal 8PinXTAL_OUT 10PinVCTRL H:PLL ON L:PLL OFF PLL2 1/4 19PinCLK384FS output (18.432MHz) 18PinCLK512FS output (24.576MHz) VCXO PLL0 1/4 24PinCLK54M output (54.0000MHz)
1: VDD54M 2: VSS54M 3: FSEL 4: TEST 5: AVDD 6: AVSS 7: XTAL_IN 8: XTAL_OUT
24: CLK54M 23: OE 22: CLK768FS 21: VDD 20: VSS 19: CLK384FS 18: CLK512FS 17: VDD_B 16: BUF_IN 15: VSS_B 14: BUF_OUT1 13: BUF_OUT2
1/8
1/6
23PinOE
H:output enable L:L out 12PinVCXO_OUT output (27.0000MHz)
9: VDD_V 10: VCTRL 11: VSS_V 12: VCXO_OUT
16PinBUF_IN (27MHz)
14PinBUF_OUT1 output (CL=50pF27MHz) 13PinBUF_OUT2 output (CL=50pF27MHz)
Fig.77 Block diagram Pin function Pin No. Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 VDD54M VSS54M FSEL TEST AVDD AVSS XTAL_IN XTAL_OUT VDD_V VCTRL VSS_V VCXO_OUT BUF_OUT2 BUF_OUT1 VSS_B BUF_IN VDD_B CLK512FS CLK384FS VSS VDD CLK768FS OE CLK54M
Fig.78 Pin assignment
Function Power supply for CLK54M output GND for CLK54M output FS select (CLK768FS selection) (FSEL=L: 44.1 kHz, FSEL=OPEN: 48 kHz, equipped with pull-up resistor) TEST pin, normally "OPEN", equipped with pull-down resistor) Power supply for PLL Analog GND for PLL Analog Crystal oscillator input pin Crystal oscillator output pin Power supply for VCXO VCXO control input pin GND for VCXO Monitor pin for VCXO output BUFFER output pin BUFFER output pin GND for BUFFER BUFFER input pin Power supply for BUFFER 24.576 MHz output 18.432MHz output GND for PLL Logic Power supply for PLL Logic FSEL=L: 33.8688 MHz output, FSEL=OPEN: 36.864 MHz output Output enable pin L: POWER DOWN, OPEN: NORMAL, equipped with pull-up resistor 54MHz output
11/16
Audio Clock Functions 1) Output phase relation The Audio clocks (i.e., CLK768FS, CLK384FS, and CLK512FS) of the BU2365FV are designed so that these clocks will intentionally becomes out of the phase of each output, in order to provide low jitter and noise levels. Thus, overlapped through currents generated at the clock edges can be suppressed to provide low jitter and noise levels. For the generation of CLK384FS (18.432 MHz), generate two-phase CLK768FS (36.864 MHz) first. The CLK768FS1 and CLK768FS2 will get to the phase relation with one clock out of the PLL2 output (VCO=147.456 MHz). By dividing the frequency in sync with the leading edge of this CLK768FS1, the CLK384FS will fall out of the phase of the CLK768FS2. Since the frequency of CLK512FS is divided into six portions in sync with the trailing edge of the PLL2 output, the CLK512FS will fall out of the phases of CLK768FS and CLK384FS by half cycle. As described above, the Audio clocks of the BU2365FV fall out of the phases each other, thus providing low jitter and noise levels. Furthermore, the true values of phase difference (Delay rate) between CLK384FS and CLK768FS are specified as shown below with consideration given to variations in the measurements on the tests before shipment. MIN 17.0 TYP 20.0 MAX 23.0
True value [nsec]
BU2365FV
DQ CLK768FS136.864MHz(inside) QB
CLK384FS18.432MHz
DQ QB PLL2 VCO147.456MHz
DQ QB
CLK768FS236.864MHz output
PLL2147.456MHz CLK768FS136.864MHz CLK768FS236.864MHz CLK384FS18.432MHz CLK512FS24.576MHz Delay
Fig.79 Audio Clock Output Circuit Configuration and Timing Chart 2) Half-pulse clock protection [HPC]
The CLK768FS output is provided with a function used to prevent the occurrence of asynchronous droop of half cycle or less (i.e., half-pulse clock) while in frequency selection under the FSEL pin control. This function is designed to set the frequency to output L fixed after the elapse of two trailing clocks of output before the selection and to a desired frequency after the elapse of two trailing clocks of output after the selection, when switching the FSEL pin. Specifically speaking, when the FSEL pin is set to High, the CLK768FS outputs a frequency of 36.864 MHz. With this setting, if the FSEL pin is switched to Low, the CLK768FS will be set to L Fixed after the lapse of two trailing clocks of 36.864 MHz, and then the CLK768FS will output a frequency of 33.8688 MHz after the lapse of two trailing clocks of 33.8688 MHz.
FSEL 36.864MHz 33.8688MHz CLK768FS output H/Lchange

H/Lchange

36.864Hz output
OutputL
33.8688MHz output
outputL
36.864MHz output
Fig.80 HPC timing chart
12/16
Package Outline
BU2365FV
Lot No.
Fig.81 Equivalent circuit PIN No.
323 (With pull-up) 4 (With pull-down )
To the inside of IC
Equivalent circuit of I/O
PIN No.
1314 1819 2224
Equivalent circuit of I/O
From the inside of IC
10
7
To the inside of IC
To the inside of IC
16
8
To the inside of IC
From the inside of IC
13/16
Application Circuit
1:VDD54M 2:VSS54M L33.8688MHz OPEN36.8640MHz 3:FSEL 4:TEST 5:AVDD BU2365FV 6:AVSS 7:XTAL_IN 27.0000MHz 8:XTAL_OUT 9:VDD_V 0.0VVDD 10:VCTRL 11:VSS_V 27.0000MHz 12:VCXO_OUT
24:CLK54M 23:OE 22:CLK768FS 21:VDD 20:VSS 19:CLK384FS 18:CLK512FS 17:VDD_B 16:BUF_IN 15:VSS_B 14:BUF_OUT1 13:BUF_OUT2
54.0000MHz (CL=15pF) OPEN=enable L=power down FSEL=L33.8688MHz FSEL=OPEN36.864MHz (CL=32pF)
18.432MHz (CL=32pF) 24.576MHz (CL=15pF)
27.0000MHz
27.0000MHz (CL=50pF) 27.0000MHz (CL=50pF)
Fig.82
Note) 1) 2)
3) 4)
5) 6) 7)
8)
Basically, mount ICs to the substrate for use. If the ICs are not mounted to the substrate, the characteristics of ICs may not be fully demonstrated. Mount 0.1uF capacitors in the vicinity of the IC pins between 1PIN (VDD54M) and 2PIN (VSS54M), 5PIN (AVDD) and 6PIN (AVSS), 9PIN (VDD_V) and 11PIN (VSS_V), 17PIN (VDD_B) and 15PIN (VSS_B), and 21PIN (VDD) and 20PIN (VSS), respectively. For the fine-tuning of frequencies, insert several numbers of pF in the 7PIN and 8PIN to GND. The electrical characteristics have been all evaluated with the use of the crystal oscillator NX5032GA (Spec. No. EXS00A-00278) manufactured by NIHON DEMPA KOGYO CO., LTD., under the conditions of Limiting resistance Rd=30 and Load CL=10pF. Consequently, in order to use the BU2365FV, the said crystal oscillator is recommended. As to the jitters, the TYP values vary with the substrate, power supply, output loads, noises, and others. Besides, for the use of the BU2365FV, the operating margin should be thoroughly checked. Depending on the conditions of the substrate, mount an additional electrolytic capacitor between the power supply and GND terminal. For EMI protection, it is effective to put ferrite beads in the origin of power supply to be fed to the BU2365FV from the substrate or to insert a capacitor (of 1 or less impedance), which bypasses high frequency desired, between the power supply and the GND terminal. Even though we believe that the example of the application circuit is worth of a recommendation, please be sure to thoroughly recheck the characteristics before use.
14/16
Cautions on use (1) Absolute Maximum Ratings An excess in the absolute maximum ratings, such as applied voltage (VDD or VIN), operating temperature range (Topr), etc., can break down devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc. (2) Recommended operating conditions These conditions represent a range within which characteristics can be provided approximately as expected. The electrical characteristics are guaranteed under the conditions of each parameter. (3) Reverse connection of power supply connector The reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown due to the reverse connection, such as mounting an external diode between the power supply and the IC's power supply terminal. (4) Power supply line Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines. In this regard, for the digital block power supply and the analog block power supply, even though these power supplies has the same level of potential, separate the power supply pattern for the digital block from that for the analog block, thus suppressing the diffraction of digital noises to the analog block power supply resulting from impedance common to the wiring patterns. For the GND line, give consideration to design the patterns in a similar manner. Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At the same time, in order to use an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant. (5) GND voltage Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric transient. (6) Short circuit between terminals and erroneous mounting In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the GND terminal, the ICs can break down. (7) Operation in strong electromagnetic field Be noted that using ICs in the strong electromagnetic field can malfunction them. (8) Inspection with set PCB On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress. Therefore, be sure to discharge from the set PCB by each process. Furthermore, in order to mount or dismount the set PCB to/from the jig for the inspection process, be sure to turn OFF the power supply and then mount the set PCB to the jig. After the completion of the inspection, be sure to turn OFF the power supply and then dismount it from the jig. In addition, for protection against static electricity, establish a ground for the assembly process and pay thorough attention to the transportation and the storage of the set PCB. (9) Input terminals In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminals a voltage lower than the GND respectively, so that any parasitic element will operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of electrical characteristics. (10) Ground wiring pattern If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well. (11) External capacitor In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc.
15/16
Name selection of ordered type
B
U
2
3
6
5
F
V
-
E
2
Part No.
Type
Package Type FVSSOP-B24
Packing specification E2: Reel-like emboss taping
SSOP-B24
Tape Quantity
7.8 0.2
24 13
Embossed carrier tape 2000pcs E2
(The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand)
7.6 0.3 5.6 0.2
1
12
1.15 0.1 0.1
0.65
0.1 0.22 0.1
0.3Min.
Direction of feed
0.15 0.1
1234
Reel
1234
1234
1pin
1234
1234
Direction of feed
1234
1234
1234
(Unit:mm)
When you order , please order in times the amount of package quantity.
Catalog No.08T804A '08.9 ROHM (c)
Appendix
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM CO.,LTD. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
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